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mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 1 general description the M65533FP is a cmos 3ch 8-bit 80mhz analog-to-digital converter by sub-ranging architecture for high speed video processing. it can be realized 80mhz operation by using 2 adcs in parallel. and it has pll circuit generate a stable clock locked to sync signal. it is a type of "ac" connection with internal clamp circuit and variable input range. features ?3ch 8-bit high speed a-d converters ?maximum conversion rate 80 msps(min.) ?analog input level 1.0v(typ) : 0.5 -1.5 v ?digital input ttl compatible [ vinth=1.4v ] ?digital output voh=0.7xvcc , vol=0.3xvcc [ io=4ma ] ?low power dissipation 700mw [ cl=10pf ] ?package 80 pin qfp package, 0.80mm lead pitch [ pkg size(without lead) =14mm x 20mm ] ?small input capacitance 10 pf ?built-in reference voltag vref(+)=1.5v+150/-330mv(*) vref(-)=0.5v ?built-in clamp circuit vclamp=0.5v+/-250mv(*) (*)controllable by iic bus applications ?lcd monitor ?high speed video processing recommended operating condition ?supply voltage range (typ.=3.3v) 3.15 to 3.45 v ?supply voltage range (typ.=5.0v) 4.75 to 5.25 v for 5v i/f only pin configuration(top view) shown on next page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 80 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 21 22 23 24 41 42 43 44 M65533FP #xxxxxx ver 3.0 '99- 5- 31
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 rnb rcin nc avddr agndr rvrt rvrm rvrb agndg gvrt gvrm gvrb bnb bcin nc avddb gnb gcin nc avddg dor7 dvddr(out) dvddg(out) dgndb(out) dog7 dgndg(out) dob7 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 64 71 70 69 68 67 66 65 80 78 76 75 74 73 72 79 77 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 21 22 23 24 34 35 36 37 38 39 40 25 27 29 30 31 32 33 26 28 dor6 dor5 44 43 42 41 agndb bvrt bvrm bvrb dvddb(out) pin configuration 2 dor4 dor3 dor2 dor1 dor0 dog6 dog5 dog4 dog3 dog2 dog1 dog0 dob6 dob5
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 block diagram ladder resistors comparators(1) comparators(2) sw mux & demu x delay & error correctio n ladder resistors comparators(2) sw mux & demu x delay & error correcti on 1st adc ( r signal ) 2nd adc ( g signal ) pll rvrt rvrb fh-in clk-out filter avddr dvddr(a/d) dvddr(out) agndr dgndr (a/d) fh fclk timing gen. ffbin rvrm dgndr(out) 3 iic bus rnb sda scl ext-clk in vdd(pll) gnd(pll) sw reset dvdd(i/o 5) dgnd(i/o 5) dvdd(lo) dgnd(lo) test1-3 cp-in dly-hdout dor0 dor1 dor2 dor3 dor4 dor5 dor6 dor7 comparators(1) (note) pins for adc is described for only r signal rc in 3rd adc ( b signal )
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 1600 3.15 3.30 3.45 2.4 vdd 0 0.8 6.25 6.25 5 v 5 absolute maximum ratings (ta = 25?, unless otherwise noted.) symbol parameter condition ratings unit dvdd digital supply voltage avdd analog supply voltage v id digital input voltage i out analog output current pd power dissipation topr operating temperature tstg storage temperature v v v ma mw ? ? 0 to 4.0 0 to 4.0 0 to 4.0 -30 to 0 0 to +70 -40 to +150 in current measurement, (+) and (-) is corresponding to an inflow and an outflow current, respectively. recommended operating conditions (ta = 25?, unless otherwise noted.) symbol parameter limits min. typ. max. unit vdd supply voltage v v ih digital input voltage (high) v il digital input voltage (low) v t wh t wl t su t h clock pulse width (high) clock pulse width (low) set-up time hold time ns ns ns ns 4 vdd((i/o) i/o supply voltage v 0 to 6.0 4.75 5.0 5.25 vdd(i/o) supply voltage(i/o) v - - - - - - - - - -
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 5 bits lsb lsb 8 3.15 3.30 3.45 vdd 0 1.5 ?1.0 0.7xvdd 10 vref(+)=1.5v, vref(-)=0.5v 1.0 electrical characteristics (ta = 25?, avdd = dvdd = 3.30v, unless otherwise noted.) symbol parameter condition limits min. typ. max. unit res resolution vdd supply voltage v nl integral nonlinearity dnl differential nonlinearity v oh v ol digital output voltage "h" digital output voltage "l" v v vina cin analog input range input capacitance vp-p pf mhz fclk max. conversion rate v vref(+) reference voltgae "high" vref(m) v vref(+)=1.5v, vref(-)=0.5v khz 10 20 80 symbol parameter condition limits min. typ. max. unit fh horizontal frequency fvco vco frequency mhz ns - jpll d.r(pll) maximum jitter pll divider ratio 0.5 800 (2) adc block (3) pll block 1.00 80 reference voltgae "middle" 120 rref ohms reference resistor symbol parameter condition limits min. typ. max. unit (1) overall ma ma aidd(ad r/g/b) didd(ad r/g/g) ad(r/g/b) analog supply current ad(r/g/g) digital supply current tbf 100 1376 70 b.w mhz input bandwidth from 800 by 1 step ?1.0 ma ma didd(i/o r/g/g) didd(pll) i/o block supply current pll block supply current tbf for r/g/b signal for r/g/b signal for r/g/b signal -3db input frequency 0.5 vref(-) v reference voltgae "low" 0.3xvdd tpdlh ns output delay time(l->h) 110 tpdhl ns output delay time(h->l) tr ns output rise time tbf tf ns output fall time tbf changeable by iic (16mv step) 1.17 1.65 0.67 1.15 0.5 vclamp v clamp voltage 0.25 0.73 0.84 1.07 changeable by iic (16mv step) didd(lo) logic block supply current didd(i/o 5) 5v i/o block supply current tbf tbf tbf tbf 60 1.0 ma ma 110 160 160
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 pin description -1 no connection. it is grounded during actual use. 6 pin no. pin name i/o function dvddx(a/d) analog power supply (r/g/b signal) clk-out o clock output fh-in h sync input from sync sep. lsi filter from or to pll filter 3.3v avddx(a/d) digital power supply (r/g/b signal) i/o power supply (r/g/b signal) dvddx(out) dox<7:0> digital output (r/g/b signal) to logic lsi to logic lsi sda scl iic data input/output iic clk input reset reset signal input 3.3v 3.3v from mcu i i/o i/o i o ext-clk in external clock intput from pll lsi pll power supply vdd(pll) 3.3v 31,33,35 dgndx (a/d) agndx (a/d) digital ground (r/g/b signal) analog ground (r/g/b signal) gnd gnd dgndx(out) i/o ground (r/g/b signal) gnd gnd(pll) pll ground gnd from mcu (r+c)//c to vdd i test<1-3 > test terminal i/o reference voltage(+) input (r/g/b signal) bypass capacitor xvrt xvrm reference voltage(m) input (r/g/b signal) reference voltage(-) input (r/g/b signal) xvrb bypass capacitor bypass capacitor adc operating current setting bias xnb bypass capacitor 5,13,21 44,54,64 66,67 30,32,34 4,12,20 45,55,65 69,70 2,10,18 7,15,23 6,14,22 1,9,17 8,16,24 46 - 53 74 68 29 79 78 80 77 25,26,27 36 - 43 56 - 63 i xcin r/g/b signal clamp input from lpf
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 pin description -2 no connection. it is grounded during actual use. 7 pin name i/o function dvdd(i/o 5) digital power supply (logic) from or to 5v dvdd (lo) digital power supply (5v) 3.3v delayed hd output dly-hd out to logic lsi o dgnd (i/o 5) dgnd (lo) digital ground (5v) digital ground (logic) gnd gnd cp-in clamp pulse input i from sync sep. lsi pin no. 76 72 73 71 75 28 3,11,19 gnd or open dly-hd out nc
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 table of power-down function( subadd=00h, d2-d0) setting by iic bus power-down function "hhh" "lll" power-down normal operation cp signal cp function "h" "l" clamping hold state table of digital output r/g/b < 7 : 0 > function setting by iic bus 0 lsb 1 2 3 4 5 6 7 msb 1 digital output code 0.500v 0.504v 0.996v 1.000v 1.496v 1.500v analog input voltage table of cp function (subadd=11h, d0) setting by iic bus 8 note hsync function d0="h" d0="l" table of hsync function(subadd=17h, d0) setting by iic bus clk output function d0="h" not-inversed ( 0 ) inversed (180 ) table of clk output function(subadd=13h, d0) setting by iic bus not-inversed inversed clk output function d5="h" d5="l" external internal table of internal/external clk(subadd=16h, d5) setting by iic bus output "hz" is available at d1="h" of subadd=18h "l"=default d0="l" only clamp=>"hll" only pll=>"lhl" only adc=>"llh" default default default default cp signal cp polarity inversed not-inversed d0="h" d0="l" digital input code digital input code digital input code digital input code digital input code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 9 table of delay adjustment(subadd=16h, d3-d0) for external clk (subadd=16h, d5="h") d3 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 0ns 5ns 35ns 40ns 70ns 75ns setting by iic bus default d2 d0 digital input code clk delayed adjustment d1 table of vref(+) voltage adjustment (subadd=0bh, d4-d0:r 0ch, d4-d0:g 0dh, d4-d0:b) 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 digital input code -84lsb -80lsb -24lsb -20lsb 36lsb 40lsb vref(+) adjustment note d3 setting by iic bus 1.5+0.157v 1.5-0.329v 1 0 1 0 1 0lsb default 0 0 1 1 1 0 d4 d2 d1 d0 1.5-0v
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 10 table of clamp level adjustment (subadd=0eh, d4-d0:r 0fh, d4-d0:g 10h, d4-d0:b) d4 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 digital input code -64lsb -60lsb -4lsb 0lsb 56lsb 60lsb delay adjustment level note setting by iic bus default d3 d1 d0 d2 0 0 0 1 1 1 0.5v+235mv 0.5v-0mv 0.5v-251mv table of clk output phase (subadd=12h, d4 -d0) 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 digital input code clk output phase d3 setting by iic bus default 0 0 1 1 1 0 d4 d2 d1 d0 digital input code clk's pol. d6="h" d6="l" nega posi table of clk's pol. for a/d (subadd=12h,d6) setting by iic bus digital input code clk output phase function d5="h" d5="l" off on table of clk output phase function (subadd=12h,d5) setting by iic bus 0 + 0 * 360/32 division into 32 of 1 period
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 11 1 0 0 1 digital input code divider adjustment a5 a3 a2 a4 1 a6 a1 a0 a3 a2 a1 a0 14h 15h 0 0 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 0 0 table of pll divider adjustment (subadd=14h,a6-a0 15h,a3-a0) setting by iic bus digital input code pll pre-divider adjustment d6,5="1 1" d6,5="1 0" 1/6 1/4 d6,5="0 1" d6,5="0 0" 1/3 1/2 table of pll divider adjustment (subadd=15h,a6-a5) setting by iic bus o/p frequency [mhz] 1/2 1/6 1/3 1/4 fh x 1376 fh x 1375 fh x 1024 fh x 1023 fh x 801 fh x 800 20 30 40 60 80
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 reset signal reset function "l" "h" reset normal operation table of reset function (pin 80) 12
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 application examples 14 input level :0.7vp-p(typ.) 0.55vp-p(min.) 0.85vp-p(max.) digital data output < 7:0 > voh=2.3v(min.), vol=1.0v(max.) t t o o l l o o g g i i c c l l s s i i f f r r o o m m p p c c o o u u t t p p u u t t clk output voh=2.3v(min.), vol=1.0v(max.) r-in g-in b-in vdd=3.3v(typ.)&5v(*) iic(**) bus fh-in & cp-in(**) (*) in case of 5vi/f (**) iic&fh-in are available for 5vi/f. lpf & output buffer M65533FP 3ch 8bit 80mhz a/d converters pkg:80pinqfp mcu m52347fp sync processor pkg:20p2n
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 13 notes to the operation 1. both a ground and a supply planes in a pcb should be as wide as possible for reducing a parasitic inductance and resistance. especially, for the better performance, the analog plane needs to be much wider. 2. a tantalum or electrolytic capacitor of 10? or more and a ceramic capacitor of 0.01? are tied together, which are connected between a digital supply and ground, also between a analog supply and ground. these capacitors should be placed as close as possible to the ic. they work as bypass capacitors for preventing a degradation in the performance by a supply voltage fluctuation caused by digital signals including a clock and digital inputs and so on. 3. the analog output should be isolated as much as possible from a clock and digital inputs, thus minimizing decoupling and interactive noise. analog input / digital output timing diagram xc in controllable by iic bus clk(int) n n-1 n-2 n-7 n-8 n-9 sampling timing dox<7:0> tpd delay cycle = 8 clocks tr, tf fh-in n+8 n
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 15 application example (M65533FP)
mitsubishi M65533FP 3ch 8-bit 80mhz a/d converters mitsubishi analog ics ( / ) 16 3-0 16 M65533FP iic-bus control table (1) slave address : a6 a5 a4 a3 a2 a1 a0 r/w 1 0 0 1 1 1 0 0 (=9ch) s slave address a a a p sub address data byte start condition acknowledge bit stop condition (2) salve address format : read (3) sub address byte and data byte format : read block no. functions bit sub add data byte d7 d6 d5 d4 d3 d2 d1 d0 1 3 00h 0 a00 5 10h 3 14h 0 5 15h 0 a05 a03 a02 a01 a00 2 a00 16h 0 17h 0 2 6 7 8 power-down clamp-in pol 4 pll upper int/ext clk h_sync pol pll lower & divider 6 7 a03 a02 a01 a00 total adc clk /pll adc output 1 18h 0 11h 0 clk phase 1 a00 12h 0 clkout pol 7 a03 a02 a01 a00 a05 5 a01 a02 10 11 12 9 14 15 13 vref(+) vol (r) vref(+) vol (g) vref(+) vol (b) clamp vol (r) clamp vol (g) clamp vol (b) 5 5 5 5 5 1 a03 a02 a01 a00 a04 a03 a02 a01 a00 a04 a03 a02 a01 a00 a04 a03 a02 a01 a00 a04 a03 a02 a01 a00 a04 a03 a02 a01 a00 a04 a00 a03 a02 a01 a00 a04 a05 a06 a01 0 0 0 0 0 0 0 0bh 0ch 0dh 0eh 13h 0fh (note) blanks shoud not be defined. becuase it may be used for test mode or function check. a06 a04 a05 a06

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